At ISCAS 2026, Huawei’s He Tingbo announced that the upcoming Kirin flagship chip will debut logic folding technology, reaching a peak frequency above 3GHz – a first for a mass‑produced smartphone SoC. The company also introduced its own Tao Law (τ) , shifting from geometry‑based scaling to time‑domain scaling as an alternative to Moore’s Law.

The new Kirin 2026 (tentative name) achieves 53.5% higher transistor density (238MTr/mm²), 41% better P‑core efficiency, and 12.7% higher peak frequency (3.1GHz) compared to traditional 2D chips. Huawei plans to push multi‑layer folding over the next decade, targeting >400MTr/mm² and 5.0GHz by 2031.

ICgoodFind: Huawei’s logic folding and Tao Law break the 3GHz barrier, offering a new path beyond Moore’s Law for advanced chip design.